1. Technical Field
The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package manufactured by stacking two or more semiconductor chips.
2. Related Art
In the semiconductor industry, packaging technology is continuously being improved to satisfy demands for miniaturization and mounting reliability of integrated circuits. For example, the demand for miniaturization has expedited the development of techniques for a package having a size approaching that of a chip size, and the demand for mounting reliability has highlighted the importance of packaging techniques for improving the efficiency of mounting work and mechanical and electrical reliability after mounting.
As miniaturization and high performance are demanded in electric and electronic products, new techniques for providing a semiconductor module having a high capacity should be developed. One method for providing a semiconductor module have a high capacity includes the high integration of a memory chip. A high integration of a memory chip can be accomplished by integrating an increased number of cells in the limited space of the semiconductor chip.
However, high integration of a memory chip requires high precision techniques, such as a fine line width, which may require a lengthily development period. Under these situations, a stacking technique has been suggested as another method for providing a semiconductor module having high capacity.
The stacking techniques can generally be divided into methods of embedding two stacked chips in one package and methods of stacking two separate packages which are independently packaged. However, the method of stacking two separate packages is limited in how much the method can decrease the height of the stacked semiconductor package. Thus, the method of stacking to separate package will have difficulties meeting the trend toward miniaturization of electric and electronic products. Therefore, a stack package or a multi-chip package realized by embedding at least two semiconductor chips in one package has been actively studied.
This chip stack package is advantageous in miniaturization and weight reduction in terms of a size, a weight and a mounting area, as compared with a single package in which a single semiconductor chip is embedded therein.